I am setting values to sequence_item before I call start_item(seq_item) any different from setting values after calling start_item(seq_item)? A sequence is executed by calling its start method, either directly or invocation of any of the `uvm_do_* macros. Kiran, You may like to refer the post titled “Application of Virtual Interface and uvm_config_db” for detailed information on “How a virtual interface inside a Config Object is connected to the actual Interface”. Note that you have to always pass the handle to a sequencer which should execute this sequence, whereas the other arguments are optional. Remember to call the `uvm_update_sequence_lib_and_item macro to update the database. Use uvm_sequence_utils. The uvm_sequence_base class provides the interfaces needed to create streams of sequence items and/or other sequences. UVM Sequence. In reply to mpattaje:. It can be configured to create and execute these sequences any number of times using one of several modes of operation, including a user-defined mode. wait_for_clock() function is just called from the Config Object. The uvm_sequence_library is a sequence that contains a list of registered sequence types. There can be no delays between start_item() and finish_item(). This macro maybe deprecated in the future. A sequence generates a series of sequence_item’s and sends it to the driver via sequencer, Sequence is written by extending the uvm_sequence. verilog verification system-verilog uvm share | improve this question virtual task start (uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence = null, int this_priority =-1, bit call_pre_post = 1); . Depending on how your driver is set up, you can either have finish_item() block until the driver issues item_done(), or you can have the sequence use get_response() waiting for the driver to … Another way to accomplish the same task is to use the macro `uvm_sequence_utils for the sequence and `uvm_sequencer_utils for the sequencer while registering with the factory.